1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) switching system, and more particularly, to an ATM cell transmitting/receiving device using an AAL2 (ATM adaptation layer 2).
2. Description of the Background Art
FIG. 1 is a schematic block diagram of an ATM cell transmitting device using an AAL1 in accordance with a conventional art.
With reference to FIG. 1, a time switch 1 serves to switch a 64 Kbps time slot. An SAR (segmentation and reassembly) controller 2 ressembles a plurality of time slots to form an ATM cell or segments the ATM cell to a plurality of time slots by using an AAL1 protocol, so as to form an ATM cell.
A buffer 3 serves to disconnect CPU of the SAR controller 2 and that of a controlling unit 5 when they concurrently accesses an SRAM 4. The SRAM 4 stores a time slot data provided from the SAR controller 2 and a control data of the controlling unit 5.
A control logic 7 generates a signal to access the first buffer unit 6, a second buffer unit 9 and a CAM 8, and the CAM (Content Addressable Memory) 8 stores a VPI (Virtual Path Identifier)/VCI (Virtual Channel Identifier) which corresponds to the time slot number in a look-up table form.
The controlling unit 5 writes a control data of the SAR controller 2 in the SRAM 4 and inserts and clears input/output data of the CAM 8 when a call is connected and released.
The first buffer unit 6 temporarily stores an ATM cell outputted from the SAR controller 2 and the control logic 7, and the second buffer unit 9 temporarily stores an ATM cell to be transmitted to an ATM network (not shown) or an ATM cell received from the ATM network.
The operation of the ATM cell transmitting/receiving device in accordance with the conventional art constructed as described above will now be explained with reference to the accompanying drawings.
1) ATM Cell Transmitting Operation
When a call is connected, time slot data switched by the time switch 1 are sequentially stored in the SRAM 4 through the SAR controller 2 and the buffer 3.
Once 256 time slot data are stored in the SRAM 4, the SAR controller 2 reads again the time slot data stored in the SRAM 4 to form an ATM cell. That is, the SAR controller 2 assembles the time slot data to an ATM cell by using a AAL1 protocol, attaches a time slot number to a header of the assembled ATM cell, and outputs it to the first buffer unit 6. Accordingly, 53-byte ATM cells are sequentially stored in the first buffer unit 6.
The control logic 7 reads the time slot number of the ATM cell header from the first buffer unit 6 and outputs it to the CAM 8.
The CAM 8 outputs the VPI/VCI corresponding to the input time slot number to the control logic 7 on the basis of the VPI/VCI information and the time slot number provided from the controlling unit 5 when a call is connected.
Accordingly, the control logic 7 substitutes the time slot number with the VPI/VCI read from the CAM 8, reads a payload of the ATM cell from the first buffer unit 6 and stores it in the second buffer unit 9.
Thereafter, at the time when the 53 byte ATM cell is wholly stored, the second buffer unit 9 transmits the completed ATM cell to the ATM network.
2) ATM Cell Receiving Operation
The ATM cell transmitted through the ATM network is stored in the second buffer unit 9. When the 53-byte ATM cell is stored, the control logic 7 reads the VPI/VCI of the ATM cell header from the second buffer unit 9 and outputs it to the CAM 8, and receives a time slot number matching with the corresponding VPI/VCI from the CAM 8.
Accordingly, the control logic 7 substitutes the VPI/VCI with the time slot number read from the CAM 17, reads the payload of the ATM cell from the second buffer unit 9 and stores it in the first buffer unit 6.
When the ATM cell is stored in the first buffer unit 6, the SAR controller 2 segments the ATM cell payload to a time slot data by using the AAL1 protocol and stores it in the SRAM 4 through the buffer 3.
Thereafter, when 256 time slot data are all stored in the SRAM 4, the SAR controller 2 reads the 256 time slot data from the SRAM 4 and outputs them to the time switch 1.
In this manner, the conventional ATM cell transmitting/receiving device converts the time slot data to the ATM cell or the ATM cell to the time slot data by using the AAL1 protocol.
However, since the AAL1 allocates only one time slot to one VPI/VCI, and especially, in case of an idle data, it occupies a channel, so that bandwidth efficiency of the ATM network is degraded.